Interfaces, Ports Specifications and Connection Validation

Interfaces, Port Specifications, and Connection Validation are key in the CELUS Design Platform, designed to facilitate the connection and coordination of CUBOs. Rather than integrating various components traditionally, these features ensure CUBOs can connect and function together effectively in an electronic design.

Port and Interface specifications detail connection parameters, including Signal Maps and compatibility rules, critical for validating CUBO™ connections. This validation checks the alignment of CUBO™ Ports against specific rules to guarantee signal integrity aned functional compatibility.

This streamlined approach enables designers to develop sophisticated electronic circuits efficiently, focusing on the practical aspects of CUBO™ connectivity.

The Ports we have defined are:

• I²C
• SPI (SPI, QSPI, SPI 3 Wire)
• SDIO
• ICSP (ICSP AVR, ICSP PIC)
• GPIO
• Supply
• USB
• Clock
• Crystal
• SWD
• RF
• I²S

A CUBO™ is essentially a modular block within a circuit, characterized by its distinct functionality. While each CUBO™ performs a specific role, a comprehensive circuit requires the integration of multiple such functionalities, interconnected through Ports. This structure facilitates the assembly of complex applications by combining these modular units, each contributing its unique function to the overall system.

Ports are the way devices connect and communicate with each other, defined by specific rules and layouts called the CELUS Standard. Each Port has its own set of signals and rules that ensure devices work well together, whether within the same system (Intra) or with external ones (Inter).

When we talk about Interfaces on the Design Canvas, we're referring to these Ports in action, showing where and how connections happen in your project.

The diagram below  shows a simplified version of how a Port is defined.

 

A simplified version of how a Port is defined.

The picture below shows how Ports are defined and their signal mapping.

 

On the CELUS Design Platform, a Port represents a broad concept, which can range from a single signal to standard communication interfaces like I2C, SPI, RMII, etc.

A Port has two main parts: The Port Definitions and Port Specifications.

Here, the Port definition of Signal map defines a specific set of Signals for that particular port. This can vary from the “standard“ signals as per electrical definition. This is done to facilitate the repeatability feature of a CUBO and allow interconnection. This means some signals necessary for a port might be split into other ports. So two or more ports might have to be connected in order to enable one specific Electrical Interface.

Port Specifications refer to the settings of a Port. The Port specifications on a CUBO is the complete list of specification without distinguishing where they are used. (The previous sentence might not be important for DS user). This works on two levels: There is Node specification and Link specification. Node specification is what is unique to the Interface for one particular Functional Block. The Link Specifications are common for any branches connected to that same link. These specifications are used to check the compatibility of the ports with each other.

 

 

Compatibility defines specific set of validation rules that determines if two or more ports are compatible with each other. These Validation rules are based on the specifications including Port Types to check the compatibility. There are different rules for different specifications.

There are also dependant specifications and dependant ports in which a specification / port is necessary for another one to complete its function.

The nets which have been assigned to signals during CUBO creation will be connected upon exporting the project.

 

The Ports we have defined are:

I²C:

I²C is defined by The traditional signals we know for I²C interface along with a ground.

The Signals of I²C are:

 

Notice that VCC is not included to be part of I²C. This means the user has to connect the SUPPLY port in addition to IIC to have them working.

I²C is only compatible with another I²C port and when connecting two blocks via I²C on the CELUS Design Studio platform, users must ensure that both blocks operate under the same power supply conditions. This is because the platform's criteria for I²C matching require that interconnected blocks have compatible supply voltages. If there is a discrepancy in the power supply between the two blocks, the platform will not be able to resolve and match them successfully through I²C.

 

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UART:

Signals of UART are:

 

UART Port is only compatible with another UART port.

 

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SPI:

The condition for getting a working SPI, just like other ports is to have a separate Supply port. However, SPI (and by extent, its derivatives) have one other requirement: There should be at least one GPIO port for every SPI connection with the specification 'Functionality Flag' chosen as 'Chip Select'.

SPI Port is split into three sub-interfaces:

SPI:

Signals of SPI are:

 

SPI is only compatible with another SPI.

QSPI:

The Signals of QSPI are:

 

Signals	Function	Requirement
IO0	Data line	Required
IO1	Data line	Required
SCK	Clock line	Required
IO2	Data line	Optional
IO3	Data line	Optional
Reference	Supply	Required

 

QSPI is only compatible with another QSPI.

SPI 3 Wire:

The Signals of SPI 3 Wire are:

Signals	Function	Requirement
MOMI	Data line	Required
SCK	Clock line	Required
Reference	Supply	Required

 

SPI 3 Wire is only compatible with another SPI 3 Wire.

 

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SDIO:

The Signals of SDIO are:

Signals	Function	Requirement
CMD	Data line	Required
CLK	Clock line	Required
DAT0	Data line	Required
DAT1	Data line	Required
DAT2	Data line	Required
DAT3	Data line	Required
Reference	Supply	Required

 

SDIO is only compatible with another SDIO.

 

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ICSP:

In our Platform, ICSP exists in two Variants:

ICSP AVR:

The Signals of ICSP AVR are:

Signals	Function	Requirement
MISO	Data line	Required
SCK	Clock line	Required
MOSI	Data line	Required
RST	Data line	Required
Reference	Supply	Required

 

ICSP AVR is only compatible with another ICSP AVR.

ICSP PIC:

The Signals of ICSP PIC are:

Signals	Function	Requirement
MCLR	Data line	Required
PGD	Data line	Required
PGC	Clock line	Required
PGM	Data line	Required
Reference	Supply	Required

 

ICSP PIC is only compatible with another ICSP PIC.

 

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GPIO:

The Signals of GPIO are:

Signals	Function	Requirement
GPIO	Data Line	Required
Reference	Supply	Required

GPIO is only compatible with another GPIO.

 

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Supply:

The Signals of Supply are:

Signals	Function	Requirement
VCC	Supply rail	Required
Reference	Return path	Required

 

Supply is only compatible with another Supply.

 

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USB:

The Signals of USB are:

Signals	Function	Requirement
D+	Data line	Required
D-	Data line	Required
CC1	Channel Configuration	Optional
CC2	Channel Configuration	Optional
TX1+	Communication/Power delivery	Optional
RX1+	Communication/Power delivery	Optional
TX2+	Communication/Power delivery	Optional
RX2+	Communication/Power delivery	Optional
TX1-	Communication/Power delivery	Optional
RX1-	Communication/Power delivery	Optional
TX2-	Communication/Power delivery	Optional
RX2-	Communication/Power delivery	Optional
SBU1	Alternative mode data line	Optional
SBU2	Alternative mode data line	Optional
Reference	Supply	Required

 

USB is only compatible with another USB.

 

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Clock:

The Signals of Clock are:

Signals	Function	Requirement
Clock	Crystal/Oscillator Clock	Required
Reference	Supply	Required

 

Right now, Clock is only compatible with another Clock.

 

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Crystal:

The Signals of Crystal are:

Signals	Function	Requirement
XTAL 1	Crystal Clock	Required
XTAL 2	Crystal Clock	Required
Reference	Supply	Required

 

Right now, Crystal is only compatible with another Crystal.

 

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SWD:

Signals of this port are:

Signals	Function	Requirement
SWCLK	Clock Line	Required
SWDIO	Data Line	Required
NRST	Data Line	Optional
SWO	Data Line (Note 6)	Optional
Reference	Supply	Required

 

For now, SWD is only compatible with another SWD port.

 

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RF:

The Signals of this port are:

Signals	Function	Requirement
RF	Signal Line	Required
Reference	Supply	Optional

 

RF Ports are used for connection between High and low Frequency Radio signals. These include and are not limited to: Radio, Antenna connectors, etc.

RF is only compatible with another RF port.

 

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I²S:

Signals of this port are:

Signals	Function	Requirement
SCK(BCLK)	Clock line	Required
WS(LRCLK)	Clock line	Required
SD	Data line	Required
Reference	Supply	Required

 

I²S is only compatible with another I²S port.

 

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CAN:

Signals of this port are:

Signals	Function	Requirement
CAN H	Signal	Required
CAN L	Signal	Required
Reference	Supply	Required

 

CAN interface is only compatible with another CAN Interface.

 

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SMBus:

Signals of this port are:

Signals	Function	Requirement
SMBCLK	Signal	Required
SMBDATA	Signal	Required
SMBALERT#	Signal	Optional
Reference	Supply	Required

 

SMBus is only compatible with another SMBus Interface for now.

 

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PMBus:

Signals of this port are:

Signals	Function	Requirement
PMBCLK	Signal	Required
PMBDATA	Signal	Required
SMBALERT#	Signal	Optional
CTRL	Signal	Optional
Reference	Supply	Required

 

PMBus is only compatible with another PMBus Interface for now.

 

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PCIe

 

PCIe x1:

Signals of this port are:

Signals	Function	Requirement
PRSNT_1	Signal	Required
PRSNT_2	Signal	Required
PERST#	Signal	Required
HSOP_0	Signal	Required
HSON_0	Signal	Required
HSIP_0	Signal	Required
HSIN_0	Signal	Required
REFCLKN	Signal	Required
REFCLKP	Signal	Required
WAKE#	Signal	Optional
TCK	Signal	Optional
TDI	Signal	Optional
TDO	Signal	Optional
TMS	Signal	Optional
TRST	Signal	Optional
CLKREQ	Signal	Optional
PWRBRK	Signal	Optional
Reference	Supply	Required

 

At the moment, PCIe x1 interface is only compatible with another PCIe x1 interface.

 

PCIe x2:

Signals of this port are:

Signals	Function	Requirement
PRSNT_1	Signal	Required
PRSNT_2	Signal	Required
PERST#	Signal	Required
HSOP_0	Signal	Required
HSON_0	Signal	Required
HSIP_0	Signal	Required
HSIN_0	Signal	Required
REFCLKN	Signal	Required
REFCLKP	Signal	Required
HSOP_1	Signal	Required
HSON_1	Signal	Required
HSIP_1	Signal	Required
HSIN_1	Signal	Required
WAKE#	Signal	Optional
TCK	Signal	Optional
TDI	Signal	Optional
TDO	Signal	Optional
TMS	Signal	Optional
TRST	Signal	Optional
CLKREQ	Signal	Optional
PWRBRK	Signal	Optional
Reference	Supply	Required

 

At the moment, PCIe x2 interface is only compatible with another PCIe x2 interface.

 

PCIe x4:

Signals	Function	Requirement
PRSNT_1	Signal	Required
PRSNT_2	Signal	Required
PERST#	Signal	Required
HSOP_0	Signal	Required
HSON_0	Signal	Required
HSIP_0	Signal	Required
HSIN_0	Signal	Required
REFCLKN	Signal	Required
REFCLKP	Signal	Required
HSOP_1	Signal	Required
HSON_1	Signal	Required
HSIP_1	Signal	Required
HSIN_1	Signal	Required
HSOP_2	Signal	Required
HSON_2	Signal	Required
HSIP_2	Signal	Required
HSIN_2	Signal	Required
HSOP_3	Signal	Required
HSON_3	Signal	Required
HSIP_3	Signal	Required
HSIN_3	Signal	Required
WAKE#	Signal	Optional
TCK	Signal	Optional
TDI	Signal	Optional
TDO	Signal	Optional
TMS	Signal	Optional
TRST	Signal	Optional
CLKREQ	Signal	Optional
PWRBRK	Signal	Optional
Reference	Supply	Required

 

At the moment, PCIe x4 interface is only compatible with another PCIe x4 interface.

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